ASIC RTL Design Engineer III, Silicon
Job Description
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
- Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.
Preferred qualifications:
- Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science.
- Experience with a scripting language like Perl or Python.
- Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT.
- Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture.
- Knowledge of memory compression, fabric, coherence, cache, or DRAM.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role you will contribute in creating the micro-architecture of the mobile SOC's subsystems, integrating multiple first-party/ third-party components, and running extensive quality checks including Lint, Clock Domain Crossing (CDC), low power checks (VCLP), synthesis, and timing and power analysis. You will be able to timely deliver Subsystems and work with various cross-functional teams ( DV/DFT/PD/Power) to ensure quality.
The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.Responsibilities
- Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).
- Perform RTL coding, function/performance simulation debug, and Lint/Cyber Defense Center (CDC)/Formal Verification (FV)/
Unified Power Format (UPF) checks. - Participate in synthesis, timing/power closure, and FPGA/silicon bring-up.
- Participate in test plan and coverage analysis of the block and ASIC-level verification.
- Communicate and work with multi-disciplined and multi-site teams.
About us
Google’s mission is to organize the world‘s information and make it universally accessible and useful.
Since our founding in 1998, Google has grown by leaps and bounds. From offering search in a single language we now offer dozens of products and services—including various forms of advertising and web applications for all kinds of tasks—in scores of languages. And starting from two computer science students in a university dorm room, we now have thousands of employees and offices around the world. A lot has changed since the first Google search engine appeared. But some things haven’t changed: our dedication to our users and our belief in the possibilities of the Internet itself.