Cake 找工作

Google welcomes people with disabilities.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Zhubei, Zhubei City, Hsinchu County, Taiwan; Taipei, Taiwan.Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 2 years of experience in semiconductor failure analysis or a related process engineering role. Experience with standard failure analysis lab equipment (e.g., Curve Tracer, Focused Ion Beam (FIB), Scanning Electron Microscope (SEM)). Preferred qualifications: Experience with Chip-on-Wafer-on-Substrate (CoWoS) packaging, interconnect analysis or stress diagnostics. Experience with advanced diagnostics tools (e.g., Utilize scan diagnosis, Automatic Test Pattern Generation (ATPG)), and memory Built-In Self-Test (BIST) tools for fault isolation. Experience with CPU/TPU specializations, diagnosing architecture-specific symptoms including cache bit flips, scanning chain issues, and Serializer/Deserializer Input/Output (SerDes I/O) failures. Experience with stress diagnostics. Knowledge of semiconductor device physics, transistor operation (e.g., Fin Field-Effect Transistor/Gate-All-Around Field-Effect Transistor (FinFET/GAA)), and fabrication processes. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will help to build the System-on-a-chip (SoCs) that power these facilities by driving quality and reliability processes in High Volume Manufacturing (HVM) from an Integrated Circuit perspective. You will partner with cross-functional teams to develop HVM quality and reliability specifications while collaborating with global hardware teams, silicon design, validation, and engineering groups to ensure fleet excellence.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Perform end-to-end electrical and physical failure analysis on Central Processing Unit/Tensor Processing Unit (CPU/TPU) devices from prototype stages through manufacturing. Utilize advanced hardware and software techniques, such as Emission Microscope (EMMI) and Optical Beam Induced Resistance Change (OBIRCH), to localize defects within reasoning and memory blocks. Execute destructive techniques including delayering, cross-sectioning, and high-resolution imaging (e.g., Scanning Electron Microscope (SEM), Transmission Electron Microscope (TEM), Focused Ion Beam (FIB)) to visualize and identify physical defects. Partner with design, product, and foundry teams to interpret failure data and implement actions for design or process improvements. Generate Failure Analysis (FA) reports and develop novel workflows tailored for advanced technology nodes and three-dimensional (3D) packaging architectures. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google welcomes people with disabilities.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Zhubei, Zhubei City, Hsinchu County, Taiwan; New Taipei, Banqiao District, New Taipei City, Taiwan.Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience with software programming languages (C/C++, Python) and application processor development. Experience with AI/ML workloads, including prefill, decode, and multimodal processing steps in LLM (Large Language Model). Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, next generation memory systems, or AI hardware accelerators. Experience with power and performance modeling and activity profiling using traces from power measurements and performance monitoring counters. Experience influencing silicon or memory roadmaps through high-fidelity performance projections of emerging technologies. Experience with ML frameworks (e.g., PyTorch, JAX, TensorFlow). Experience with SQL for data querying and analysis. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Senior System Architect within the Silicon team, you will work on GenAI use cases across hardware and software. You will be responsible for modeling and analyzing trade-offs for on-device vs. cloud AI execution of Gemini AI models. This role is critical in influencing the hardware and software roadmaps for SOC, AI accelerator, and new memory technologies.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Model and estimate power and performance for next-generation SoC and memory technologies. Optimize hardware and software architectures for future GenAI use cases. Measure and compare on-device AI and cloud AI to provide guidance for Hybrid AI development. Support emerging technology initiatives with alignment across silicon process, IP design, Android OS, and Gemini model teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google welcomes people with disabilities.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: New Taipei, Banqiao District, New Taipei City, Taiwan; Zhubei, Zhubei City, Hsinchu County, Taiwan.Minimum qualifications: Bachelor's degree or equivalent practical experience. 5 years of experience in program or project management. 5 years of experience in managing SoC semiconductor manufacturing, and consumer hardware supply chain. Experience in making semiconductor production supply plans. Experience managing semiconductor vendors. Preferred qualifications: Experience with advanced supply chain visualization tools (e.g., Kinaxis, e2open, SAP). Experience mentoring junior planners or leading large-scale, cross-functional supply chain transformation initiatives. Understanding of Foundry and OSAT ecosystems, and how sub-component lead times impact the overall SoC assembly cycle. Ability to articulate complex supply chain scenarios into logical, simplified narratives for executive leadership and decision-making. About the jobA problem isn’t truly solved until it’s solved for all. That’s why Googlers build products that help create opportunities for everyone, whether down the street or across the globe. As a Program Manager at Google, you’ll lead complex, multi-disciplinary projects from start to finish — working with stakeholders to plan requirements, manage project schedules, identify risks, and communicate clearly with cross-functional partners across the company. Your projects will often span offices, time zones, and hemispheres. It's your job to coordinate the players and keep them up to date on progress and deadlines. Responsibilities Architect and oversee the mass production (MP) supply chain for system on a chips (SoC); drive seamless material flow for critical sub-components (substrates, DRAM, IPD) to ensure readiness aligns with assembly schedules while proactively mitigating capacity risks and shortages. Lead cross-functional synchronization between upstream or downstream planners, sourcing, and engineering to optimize material arrival and minimize inventory buffers. Enforce vendor excellence by monitoring performance against rigorous quality and delivery Key Performance Indicators (KPI), and drive deep-dive root-cause analysis for any supply disruptions. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google welcomes people with disabilities.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Zhubei, Zhubei City, Hsinchu County, Taiwan; Taipei, Taiwan.Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 2 years of experience in test engineering or product engineering. 2 years of experience with industry-standard tools, languages, and methodologies relevant to the development of silicon-based ICs and chips. Experience in ATE test development for New Product Introduction (NPI) or High Volume Manufacturing (HVM). Preferred qualifications: Master’s in Electrical Engineering, Computer Engineering, Computer Science, or related field. 8 years of experience in test engineering or product engineering. Experience with Scan/ATPG, Memory BIST (MBIST), or High-Speed I/O (HSIO) ATE testing, including ATE board and socket debugging. Knowledge of Automatic Test Equipment (ATE) platforms such as Advantest V93K or Teradyne UltraFlex. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will help build the Systems on Chip (SoCs) that power these data centers by developing and deploying test solutions with Automated Test Equipment (ATE) for high-volume manufacturing at wafer fabrication sites and outsourced semiconductor assembly and tests (OSATs). This is an opportunity to create silicon and follow it into the field to close the loop back to design and test for the next generation of chips. You will drive ATE manufacturing testing to validate performance and screen defective devices. You will own all aspects of ATE testing—including wafer sort, final test, and burn-in—and work with cross-functional teams to ensure optimal test coverage in production for high-quality SoCs.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Develop and implement strategies for manufacturing test of SoC products, including troubleshooting, test coverage optimization, defective parts per million (DPPM) reduction, and power and performance assurance. Participate in ATE test deployment and optimization for High Volume Manufacturing (HVM), working with the NPI product development and test team, vendors, and HVM product engineering. Collaborate with cross-functional teams globally, including ATE and SLT Test Engineering, Packaging, Supplier Management, and Operations, to build, deploy, and maintain an HVM screening solution. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google welcomes people with disabilities.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: New Taipei, Banqiao District, New Taipei City, Taiwan; Zhubei, Zhubei City, Hsinchu County, Taiwan.Minimum qualifications: Bachelor's degree in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, related degree or equivalent practical experience. 10 years of experience in the semiconductor industry. 5 years of experience managing IC qualification, production releases, and system-level testing, with a focus on data review, yield enhancement, and test time. Experience with integrated circuit (IC) testing, and in Yield and Bin Pareto analysis. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, or related degree. Experience in semiconductor processing, VLSI product or test engineering, with SLT, and using the advantest platform. Experience with ATE platforms (Teradyne UltraFlex SoC and Advantest 93K), with knowledge of high-speed interfaces (DDR, PCIe, SERDES). Understanding of design for testing (DFT) methodologies, including memory BIST, JTAG, Scan/ATPG, and testing for PVT and temperature sensors. Understanding of advanced packaging technologies such as InFO and 2.5D. Ability to utilize data analysis tools (O+, Datapower, or JMP). About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will develop and deploy comprehensive automatic test equipment (ATE) solutions for high-volume manufacturing at Fabrication Plants (FABs) and Outsourced Semiconductor Assembly and Test (OSATs). You will integrate SoC technologies into devices and facilitate ATE testing to validate performance and screen units. You will lead all testing aspects, collaborating with cross-functional teams to ensure optimal production coverage and high-quality SoCs.You will develop digital and mixed-signal tests, automation methodologies, and internal tools for test program management. Additionally, you will release cost-effective test solutions into mass production.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Design, implement, and manage Integrated Circuit (IC) product bring-up, verification, and characterization programs for NPI, including ATE test programs, load boards, and probe cards using ATE platforms such as UFLEX or 93K. Collaborate with vendors and internal teams to engineer high-volume ATE manufacturing solutions tailored for advanced packaging. Execute product and Defective parts per million (DPPM) correlation between ATE and system-level environments for new products. Enhance test coverage and resolve various failure modes via troubleshooting on ATE and System Level Testing (SLT) systems. Direct production sustaining activities, including program upgrades, yield optimization, test time reduction, lot disposition, and Return Merchandise Authorization (RMA) analysis. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google welcomes people with disabilities.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: New Taipei, Banqiao District, New Taipei City, Taiwan; Zhubei, Zhubei City, Hsinchu County, Taiwan.Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering or Computer Science, emphasizing in Computer Architecture, or equivalent practical experience. 4 years of experience in microprocessor architecture, microarchitecture, performance, or advanced CPU design. Experience with C/C++ and scripting languages (e.g., Python). Experience in CPU architecture, performance modeling, analysis, correlation, and workload characterization. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science, emphasizing in Computer Architecture or Machine Learning. Experience in CPU/ML microarchitecture exploration, performance model development, performance analysis, performance correlation, or workload characterization. Knowledge of microprocessor instruction set architecture (e.g., ARM, RISC-V, x86). Familiarity with system software components, such as Linux, drivers, and runtime. About the jobAs a CPU Performance Architect, you will be the key contributor to improve processor instruction set architecture, to develop innovative microarchitecture features, and deliver Google’s advanced SoC products. You will collaborate cross-functionally with Android Applications and AI teams to conduct applications and benchmark performance analysis and to project their performance at various design phases. You will be guided by architects and work with engineers in Power, Thermal, Security, and Physical Design teams to determine the CPU subsystem configuration and features.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Develop and modify a performance model for performance analysis and microarchitecture study. Evaluate Advanced RISC Machine (ARM’s) architecture features from both architecture and performance angles. Define and write CPU subsystem architecture specifications. Collaborate with Register-Transfer Level (RTL), design verification, and physical design teams to develop a high-performance and efficient CPU implementation. Manage performance correlation between the performance model and RTL implementation, including micro-benchmark development and pre-silicon and post-silicon performance bug triage. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google welcomes people with disabilities.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: New Taipei, Banqiao District, New Taipei City, Taiwan; Zhubei, Zhubei City, Hsinchu County, Taiwan.Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience in functional verification, performance validation, developing test plans and diagnostic codes of modern processors. Experience with processor microarchitecture. Preferred qualifications: Master degree in Electrical Engineering, Computer Science or related fields. Experience with UVM, SystemVerilog, or other scripting languages such as Python, Perl, Shell, Bash, etc. Experience with ARM Instruction Set Architecture. Knowledge of general purpose operating systems such as Linux and Android. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Design verification for future CPU developments. Build functional verification infrastructure, the infrastructure will include unit, multi-unit, core, and subsystem level verification environments. Produce diagnostic code repositories that sufficiently enable production of quality CPU’s. Verify and validate performance for both pre-silicon and post-silicon. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google welcomes people with disabilities.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: New Taipei, Banqiao District, New Taipei City, Taiwan; Zhubei, Zhubei City, Hsinchu County, Taiwan.Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience with computer architecture concepts, including micro architecture, cache hierarchy, pipelining, and memory subsystems. 3 years of experience working with Mobile or Embedded SoCs architecture or use case system design. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science. 5 years of experience working with Mobile or Embedded SoCs related to system design to improve use case level power and performance. Experience driving system architecture decisions across SW/HW teams within an organization to build up the consensus and translate ideas into architecture specifications. Experience with Android Architecture, Mobile SoC architecture, ML architecture, Computer Architecture, PPA trade-offs. Knowledge of interactions between software and HW IP blocks, general and special purpose compute units. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As part of the Platform System Architecture team, you will leverage the expertise in computer and AI/ML architecture, Power, Performance, and Area (PPA) trade-offs, mobile SoC AI/ML workloads analysis, ability to traverse across the Software (SW)/Hardware (HW) stack to influence IP and SoC architecture for the Tensor SoC to bring in the latest AI/ML user experience on Pixel devices.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Influence Tensor SoC architecture decisions for PPA working cross-functionally with SW/HW architects, design teams, and research teams to enable the industrial best user experience on Pixel phone devices empowered by the latest and the most advanced Generative AI technologies provided by Google research. Leverage a data driven approach through profiling, simulation and modeling, drive consensus around architectural decisions across the entire silicon organization to solve system design problems. Be the primary owner of the architecture specifications, system design documentation, workload analysis, modeling and projection to influence and define future SoC architecture. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google welcomes people with disabilities.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Zhubei, Zhubei City, Hsinchu County, Taiwan; Taipei, Taiwan.Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 2 years of experience in Product or Yield Engineering. 2 years of experience with interpreting ATE data logs (V93K, UltraFLEX), physical failure analysis and yield improvement. Preferred qualifications: Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. 8 years of experience in product engineering, including test engineering. Experience evaluating customer returns with ATE and SLT, identifying coverage gaps, developing incremental structural and functional patterns to address quality issues. Experience in Python or Perl for data automation, statistical analysis (e.g., JMP), and yield management systems. Experience in leadership delivering screening solutions for the computing chips in advanced technology nodes with low DPPM. Knowledge of industry standards, design tools, and DFT best practices, including at-speed TDF, ATPG, MBIST, Memory Repair, diagnostic tools, yield improvement. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a SoC Product Engineer, you will design and build the systems that form the foundation of the world's largest and most powerful computing infrastructure. You will develop from the lowest levels of circuit design to large system design and see those systems all the way through to high-volume manufacturing and mission-mode operation. You will work to shape the machinery that goes into our data centers affecting Google users.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Develop and implement strategies for high-volume manufacturing of SoC products, including troubleshooting, ATE test coverage optimization, Defective Parts Per Million (DPPM) reduction, power and performance assurance, and product data integration and correlation between system, ATE, and SLT. Drive interactions with wafer Fabrications (fabs) and Outsourced Semiconductor Assembly and Test (OSATs), and own and drive checkpoints for the quality metrics. Drive production through test program releases, volume data analytics, lot disposition, extended test time reduction, yield improvement, and Return Materials Authorization (RMA) management. Own setup and maintenance of test, diagnosis, and yield analysis infrastructure, including RMA support. Collaborate with cross-functional teams across the globe, including Automated Test Equipment (ATE) and System-Level Test (SLT) Test Engineering, Packaging, Supplier Management, and Operations, to build, deploy, and maintain a high-volume manufacturing screening solution. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google welcomes people with disabilities.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Zhubei, Zhubei City, Hsinchu County, Taiwan; Taipei, Taiwan.Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 2 years of experience in product engineering or test engineering. Experience in System-Level Test development for NPI or High-Volume Manufacturing. Experience with Linux/Unix, Python programming, and TCP/IP network configuration. Preferred qualifications: Master's degree in Electrical Engineering, Computer Engineering or Computer Science. 8 years of experience with hardware and semiconductor testing. Experience implementing secure ASIC/SoC manufacturing solutions, including Manufacturing Execution System (MES) and System-Level Test (SLT) handler. Knowledge of ASIC/SoC boot process, boot loader development, or CPU performance testing. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.The team designs and builds the hardware, software, and networking technologies that power all of Google's services.In this role, you will design and build the systems in computing infrastructure. You will develop from the lowest levels of circuit design to system design and see those systems all the way through to high-volume manufacturing and mission-mode operation.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.Responsibilities Develop and implement strategies for manufacturing tests of SoC products, including troubleshooting, test coverage optimization, power and performance assurance. Lead System-Level Test (SLT) deployment and optimization for manufacturing, working with the NPI team, vendors, and product engineering. Identify and separate test versus design/process yield loss; debug and solve test-related failures through software (e.g., test, automation), hardware (e.g., test fixture, handler, networking/communication), and operational improvements. Develop, debug, and optimize SLT test content for manufacturing screening. Collaborate with cross-functional teams across the globe, including Automatic Test Equipment (ATE) and SLT Test Engineering, Packaging, Supplier Management, and Operations, to ensure System-Level Test success. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.