Quest Global

- Responsible for all front-end integration activities like Lint, CDC, Synthesis, LEC, Low Power and UPF, formal verification, STA and ECO implementation - Do Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL Physical designers to resolve them - Do Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures - Develop Timing Constraints for RTL-Synthesis and STA-Signoff for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks - Implement, enhance and maintain Synthesis, STA scripts and various automation flows - Work closely with logic design and PnR engineers on logic, timing, power and physical issues

– Responsible for Verification from Verification Strategy, Testbench Development, Verification Item List to Simulation, Coverage Analysis – Verification Strategy/Test Plan Development: Create Strategy/Plan based on Design specification/Micro Architecture – Testbench Development, Simulation/Debugging to identify and resolve any issues/failures of the design – Work closely with Synthesis/PD teams to address any defects in Netlist, Timing SDF and ensure specifications are met – Coverage analysis to detect uncovered areas that need further testing – Documentation and reporting for progress tracking, detailed feedback to design teams, verification result

– Conduct DFT Engineering Tasks: DFT Audit/Scan Logic/MBIST Logic/BSCAN Logic Insertion – Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the design – Responsible for development of innovative DFT IP in collaboration with the cross-functional teams, and play a key role in full chip design integration with the testability features integrated in RTL – Work closely with the design/design-verification and physical design teams to enable the integration and validation of the Test logic in all phases of the design, and back-end implementation flow – Analyze timing report and suggest for the solution – Skillful in gate-level simulations with and without timing annotations – Diagnose and analyze data logs during silicon bring-up phase to finalize prototype patterns – Be responsible for Innovative Hardware DFT for new silicon device models, bare die stacked die- driving re-usable test and debug strategies

– Responsible for the full physical design cycle from Synthesis to GDSII – Perform tasks like Synthesis, floor-planning, placement, CTS, routing, and timing analysis – Perform the signoff check like: STA/ EMIR (IR, DvD, P-EM, S-EM)/ PV(LVS/ANT/DRC/DFM) /Low power check ... tape-out procedures – Ensure the design meets performance, power, and area constraints – Utilize Electronic Design Automation (EDA) tools for design, simulation, and verification – Work closely with stakeholders like: Design team, constraint team, DFT team, DV team, IP team to ensure the physical layout meets design specifications – Perform physical verifications such as layout versus schematic (LVS) and design rule checking (DRC) – Conduct parasitic extraction and analysis to optimize the performance of the IC – Resolve design and flow issues related to physical design, identify potential solutions, and drive execution – Optimize designs for power, area, and performance – Stay up to date with the latest technology trends (7nm/5nm/3nm and beyond), industry standards, and EDA tools – Conduct logic synthesis, floor planning, power and clock distribution, timing optimization, signal integrity and place and route – Work closely with team members to resolve design and flow

Define and design product architecture and implement solutions for complex problemsProvide technical input to prepare project scope, schedule, estimation and costGuide and mentor the technical leads to deliver commitments on time with QualityInteract with customers on the project technical aspects and prepare and present the project technical progressReview the technical work products and ensure quality timelinessPredict project risks and develop mitigation plansTravel to India, Japan, and customer sites as neededParticipate in the hiring process, including defining job descriptions, conducting interviews, and related activities

– Responsible for Verification from Verification Strategy, Testbench Development, Verification Item List to Simulation, Coverage Analysis – Verification Strategy/Test Plan Development: Create Strategy/Plan based on Design specification/Micro Architecture – Testbench Development, Simulation/Debugging to identify and resolve any issues/failures of the design – Work closely with Synthesis/PD teams to address any defects in Netlist, Timing SDF and ensure specifications are met – Coverage analysis to detect uncovered areas that need further testing – Documentation and reporting for progress tracking, detailed feedback to design teams, verification result

Conduct DFT Engineering Tasks: DFT Audit/Scan Logic/MBIST Logic/BSCAN Logic Insertion - Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the design - Responsible for development of innovative DFT IP in collaboration with cross-functional teams, and play a key role in full chip design integration with the testability features integrated in RTL - Work closely with the design/design-verification and physical design teams to enable the integration and validation of the Test logic in all phases of the design, and back-end implementation flow - Analyze timing report and suggest for the solution - Skillful in gate-level simulations with and without timing annotations - Diagnose and analyze data logs during silicon bring-up phase to finalize prototype patterns - Be responsible for Innovative Hardware DFT for new silicon device models, bare die stacked die- driving re-usable test and debug strategies

Responsible for Analog Mixed Signal Verification + Verification Strategy/Test Plan Development: Create Strategy/Plan based on Design specification. + Develop analog RNM. + Perform simulation with RTL/Netlist and RNM. + Work closely with Synthesis/PD teams to address any defects in Netlist and ensure specifications are met. + Documentation and reporting for progress tracking, detailed feedback to design teams, verification result.