Lead/ Sr. Lead Design For Test Engineer

Conduct DFT Engineering Tasks: DFT Audit/Scan Logic/MBIST Logic/BSCAN Logic Insertion

- Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the design

- Responsible for development of innovative DFT IP in collaboration with cross-functional

teams, and play a key role in full chip design integration with the testability features integrated in RTL

- Work closely with the design/design-verification and physical design teams to enable the integration and validation of the Test logic in all phases of the design, and back-end implementation flow

- Analyze timing report and suggest for the solution

- Skillful in gate-level simulations with and without timing annotations

- Diagnose and analyze data logs during silicon bring-up phase to finalize prototype patterns

- Be responsible for Innovative Hardware DFT for new silicon device models, bare die & stacked die- driving re-usable test and debug strategies

- At least 5+ years of DFT engineering experience

- Good understanding DFT and Clock Architecture and DFT Concepts

- Experience with whole-chip DFT with different flows: fully Tessent Shell flow, hybrid flow (mixed vendor tools) …

- Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between Test quality and Test time

- Experience developing DFT specifications and driving DFT architecture and methods for designs

- Experience in debugging Compressed ATPG patterns, MBIST, and JTAG/1500 related issues

- Be able to SDC build timing constraints for SCAN, MBIST, IJTAG modes and analyze timing report

- Good knowledge of functional safety, clock domain crossing analysis, logic synthesis and scan insertion

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