Cake 找工作

Minimum qualifications: PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering or related technical field, or equivalent practical experience. Experience with accelerator architectures and data center workloads. Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools. Preferred qualifications: 2 years of experience post PhD. Experience with performance modeling tools. Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies. Knowledge of high performance and low power design techniques. About the jobIn this role, you will shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer and drive cutting-edge TPU (Tensor Processing Unit) technology that fuels Google's most demanding AI/ML applications. You will collaborate with hardware and software architects and designers to architect, model, analyze, define and design next-generation TPUs. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design, and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs. Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and RTL designs and evaluate quantitative and qualitative performance and power analysis. Partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces. Develop and adopt advanced AI/ML capabilities, drive accelerated and efficient design verification strategies and implementations. Use AI techniques for faster and optimal Physical Design Convergence -Timing, floor planning, power grid and clock tree design etc. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies, contributing to the advancement of silicon bring-up and qualification processes. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Logitech is the Sweet Spot for people who want their actions to have a positive global impact while having the flexibility to do it in their own way.EPM DEVELOPERInformation Technology  Guindy, Chennai, Tamil NaduDESCRIPTIONPosition at LogitechThe Role:The Role EPM Developer is responsible for design, development and implementation of all planning, reporting and consolidation solutions for the stakeholders in the finance department.Your Contribution:Be Yourself. Be Open. Stay Hungry and Humble. Collaborate. Challenge. Decide and just Do. These are the behaviors you’ll need for success at Logitech. In this role you will:·       Design, Develop, implement financial planning, reporting and consolidation solutions using Onestream as well as providing technical and functional guidance, assistance and support·       Employ knowledge of the EPM Suite of applications to facilitate better deployment of Planning and reporting applications in Onestream·       Desire and aptitude to be an active contributor to meetings and projects, both internal to the technology team as well as those assigned throughout the business·       Evaluate standard functionality in Onestream to leverage the system for process improvement. Re-design and develop applications and functionality as required  ·       Participate in all phases of software development with emphasis on the planning, analysis, testing, integration, documentation, and presentation phases.·       Develop test scenarios, test scripts and perform unit, system and interface testing·       Develop associated technical and functional documentation including but not limited to requirements, design, testing and user guides·       Develop custom dashboards that will generate custom integration solutions. Identify and Integrate and translate data into dashboards and actionable information to address organizational needs·       Participate in defining company’s overall reporting and analytics strategy·       Coordinate with architects and senior developers to determine functionalities. Attend and participate in project requirement meetings and work sessions and provide timely updates on the work performed                                                                                Key Qualifications:For consideration, you must bring the following minimum skills and behaviors to our team:·       A minimum of 2-4 years of EPM experience in a developer role and a minimum 6 months hand-on experience as a Onestream developer·       Strong experience as a technical resource designing and delivering Onestream solutions·       Strong functional knowledge around financial systems and processes·       Strong knowledge of SOX and implementing ITGC controls·       Interacting with business clients to understand, define, analyze, and deliver customer requirements·       Skilled in building and maintaining Business rules, scripts and develop technical solutions to complex business problems·       Ability to design, develop (code), test, and debug applications.·       Ability to provide alternatives based on best practices and application functionality·       Proficient in User interface design and developing visually appealing user interfaces·       Experience with .NET/C# and SQL coding. Should have fluency in writing in Onestream Business rules·       Skilled development of multifaceted testing plans and processes for complex systems.·       Strong oral and written communication skills, including presentation skills·       Proficient in Microsoft office productsIn addition, preferable skills and behaviors include:·       Any certification in Onestream course·       Proficient with reporting tools such as OBIEE and Tableau, and familiar with Oracle ERP and Snowflake data warehouseEducation:BS/MS in Computer Science, Information Systems or a related technical field or equivalent industry expertise.Logitech is the sweet spot for people who are passionate about products, making a mark, and having fun doing it. As a company, we’re small and flexible enough for every person to take initiative and make things happen. But we’re big enough in our portfolio, and reach, for those actions to have a global impact. That’s a pretty sweet spot to be in and we’re always striving to keep it that way.Across Logitech we empower collaboration and foster play. We help teams collaborate/learn from anywhere, without compromising on productivity or continuity so it should be no surprise that most of our jobs are open to work from home from most locations. Our hybrid work model allows some employees to work remotely while others work on-premises. Within this structure, you may have teams or departments split between working remotely and working in-house.Logitech is an amazing place to work because it is full of authentic people who are inclusive by nature as well as by design. Being a global company, we value our diversity and celebrate all our differences. Don’t meet every single requirement? Not a problem. If you feel you are the right candidate for the opportunity, we strongly recommend that you apply. We want to meet you!We offer comprehensive and competitive benefits packages and working environments that are designed to be flexible and help you to care for yourself and your loved ones, now and in the future. We believe that good health means more than getting medical care when you need it. Logitech supports a culture that encourages individuals to achieve good physical, financial, emotional, intellectual and social wellbeing so we all can create, achieve and enjoy more and support our families. We can’t wait to tell you more about them being that there are too many to list here and they vary based on location.All qualified applicants will receive consideration for employment without regard to race, sex, age, color, religion, sexual orientation, gender identity, national origin, protected veteran status, or on the basis of disability.If you require an accommodation to complete any part of the application process, are limited in the ability, are unable to access or use this online application process and need an alternative method for applying, you may contact us toll free at 1-510-713-4866 for assistance and we will get back to you as soon as possible.

Logitech is the Sweet Spot for people who want their actions to have a positive global impact while having the flexibility to do it in their own way.The Role EPM Lead Developer Anaplan will be responsible for designing, building, and optimizing enterprise-grade Anaplan models that support sales forecasting, commission planning and other critical business processes for the stakeholders in the Sales Marketing department.Your Contribution:Be Yourself. Be Open. Stay Hungry and Humble. Collaborate. Challenge. Decide and just Do. These are the behaviour’s you’ll need for success at Logitech. In this role you will:Lead end-to-end design, build, and enhancement of Anaplan models based on business requirements.Translate complex business processes into scalable Anaplan architecture.Develop UX dashboards, modules, lists, actions, and model automation.Ensure adherence to Anaplan best practices, performance optimization, and model sustainability.Serve as the technical lead for new Anaplan implementations, enhancements, and rollouts.Drive model governance, data quality management, change control, and model lifecycle standards.Mentor and guide junior Anaplan model builders and business analysts.Manage sprint planning, development timelines, and delivery quality.Collaborate with Finance, Sales, Commercial Planning, Supply Chain, and HR teams to understand planning needs.Convert business inputs into functional requirements and actionable development tasks.Conduct user testing, training, and hyper care support post-deployment.Work with IT integration teams to build and maintain data pipelines between Anaplan and ERP/CRM/Data Lake systems.Ensure data validation, mapping accuracy, and scheduled automation.Troubleshoot data and process issues proactively.Desire and aptitude to be an active contributor to meetings and projects, both internal to the technology team as well as those assigned throughout the businessDevelop test scenarios, test scripts and lead teams in unit, integration and acceptance testingDrive application development projects as assignedExperience in implementing Anaplan Data Orchestrator (ADO)Experience in implementing Polaris model, Anaplan WorkflowFunctional understanding of different sales operations, commission accrual process etc. is a must Proficient in SQL skills with the ability to understand relational data modelsAbility to tune and optimize applications for Optimal Data Load, Calculation and Query PerformanceAbility to provide alternatives based on best practices and application functionalityProficient in User interface design and developing visually appealing user interfacesSkilled development of multifaceted testing plans and processes for complex systemsKey Qualifications: For consideration, you must bring the following minimum skills and behaviour’s to our team:Overall 7 years of experience with minimum of 5 years of experience with Anaplan model buildingExtensive Experience in Anaplan Model Building with exposure to Sales Operations planning.Vast knowledge of Modules, Dashboards, Lists, processes, and experience writing complex member formulas and understanding of Data integrity between models. New UX experience. Experience working with EPM productsStrong oral and written communication skills, including presentation skillsStrong technical aptitude, with a high ceiling for further growthProficient in Microsoft office products In addition, preferable skills and behaviours include:Anaplan certification (Anaplan Certified Solution Architect)Education:BS/MS in Computer Science, Information Systems or a related technical field or equivalent industry expertise.Logitech is the sweet spot for people who are passionate about products, making a mark, and having fun doing it. As a company, we’re small and flexible enough for every person to take initiative and make things happen. But we’re big enough in our portfolio and reach for those actions to have a global impact. That’s a pretty sweet spot to be in and we’re always striving to keep it that way.Across Logitech we empower collaboration and foster play. We help teams collaborate/learn from anywhere, without compromising on productivity or continuity so it should be no surprise that most of our jobs are open to work from home from most locations. Our hybrid work model allows some employees to work remotely while others work on-premises. Within this structure, you may have teams or departments split between working remotely and working in-house.Logitech is an amazing place to work because it is full of authentic people who are inclusive by nature as well as by design. Being a global company, we value our diversity and celebrate all our differences. Don’t meet every single requirement? Not a problem. If you feel you are the right candidate for the opportunity, we strongly recommend that you apply. We want to meet you!We offer comprehensive and competitive benefits packages and working environments that are designed to be flexible and help you to care for yourself and your loved ones, now and in the future. We believe that good health means more than getting medical care when you need it. Logitech supports a culture that encourages individuals to achieve good physical, financial, emotional, intellectual and social wellbeing so we all can create, achieve and enjoy more and support our families. We can’t wait to tell you more about them being that there are too many to list here and they vary based on location.All qualified applicants will receive consideration for employment without regard to race, sex, age, color, religion, sexual orientation, gender identity, national origin, protected veteran status, or on the basis of disability.If you require an accommodation to complete any part of the application process, are limited in the ability, are unable to access or use this online application process and need an alternative method for applying, you may contact us toll free at 1-510-713-4866 for assistance and we will get back to you as soon as possible.

Minimum qualifications: 8 years of experience leading an embedded or firmware development team. Experience with embedded software or firmware development in C/C++. Experience with bringing up bare-metal environments on SoCs. Experience in leading firmware debugs on silicon and usage of debug tools such as TRACE32, OpenOCD, etc. Preferred qualifications: Experience with ARM and RISC-V architectures. Experience in using emulation platforms for firmware enablement, validation, and debug. Experience in industry standard software development practices and agile methodologies. Understanding of SoC architecture and interfaces (e.g., AXI, DDR, PCIe, etc.). About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Build, manage and lead the team responsible for firmware and infrastructure development to enable bring-up and validation of the AI/ML SoC designs. Lead and enable the team to develop embedded firmware, bare metal tests and low-level debug tools for pre and post-silicon validation of SoCs. Exercise these capabilities on emulation, simulation and silicon platforms. Co-work with architecture, design and verification teams and enable Hardware-Software co-design. Engage with the silicon design team at a very early stage and drive integration validation and firmware features enablement as the silicon development progresses. Work with post-silicon and platform hardware teams to ensure silicon enablement and support silicon debugs. Drive all the people management functions including, but not limited to, hiring, people development, prioritizing and managing resources to achieve project execution timelines. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor’s degree in Electrical Engineering or equivalent practical experience. 5 years of experience with advanced design, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs. Experience with System on a Chip (SoC) cycles. Experience in high-performance, high-frequency, and low-power designs. Preferred qualifications: Master’s degree in Electrical Engineering.Experience in coding with System Verilog and scripting with Tool Command Language (TCL).Experience in VLSI design in SoC or experience with multiple-cycles of SoC in ASIC design.Experience in coding constraints and scripting with TCL.Experience with Static Timing Analysis (STA) convergence on blocks/Subsystem (SS)/SoC About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be part of a team developing SoCs used to accelerate Machine Learning (ML) computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.Responsibilities Define and drive the implementation of physical design methodologies. Take ownership of one or more physical design partitions or top level. Manage timing and power consumption of the design. Contribute to design methodology, libraries, and code review. Define the physical design related rule sets for the functional design engineers. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience in ASIC development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL). Experience in micro-architecture and design IPs and Subsystems. Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Preferred qualifications: Experience with scripting languages (e.g., Python or Perl). Experience in SoC designs and integration flows. Knowledge of bus architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies.. Knowledge of high performance and low power design techniques. About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be part of a team developing Application-Specific Integrated Circuits (ASIC) used to accelerate and improve traffic efficiency in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Drive development of complex IPs and subsystems along with a team of engineers. Own micro-architecture and implementation of IPs and subsystems. Work with architecture, firmware and software teams to drive feature closure and develop micro-architecture specifications. Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams. Identify and drive power, performance and area improvements for the domains owned. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering or related technical field, or equivalent practical experience. Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools. Experience with accelerator architectures and data center workloads. Preferred qualifications: 2 years of experience in Silicon domain post PhD.Experience with performance modeling tools. Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies. Knowledge of high performance and low power design techniques. About the jobIn this role, you will shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer and drive TPU (Tensor Processing Unit) technology that fuels Google's most demanding AI/ML applications. You will collaborate with hardware and software architects and designers to architect, model, analyze, define and design next-generation TPUs. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design, and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.Responsibilities Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs. Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and RTL designs and evaluate quantitative and qualitative performance and power analysis. Partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces. Develop and adopt advanced AI/ML capabilities, drive accelerated and efficient design verification strategies and implementations. Use AI techniques for faster and optimal physical design convergence -timing, floor planning, power grid and clock tree design etc. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies, contributing to the advancement of silicon bring-up and qualification processes. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science. Experience with a scripting language like Perl or Python. Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture. Knowledge of memory compression, fabric, coherence, cache, or DRAM. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role you will contribute in creating the micro-architecture of the mobile SOC's subsystems, integrating multiple first-party/ third-party components, and running extensive quality checks including Lint, Clock Domain Crossing (CDC), low power checks (VCLP), synthesis, and timing and power analysis. You will be able to timely deliver Subsystems and work with various cross-functional teams ( DV/DFT/PD/Power) to ensure quality. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.Responsibilities Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform RTL coding, function/performance simulation debug, and Lint/Cyber Defense Center (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. Participate in test plan and coverage analysis of the block and ASIC-level verification. Communicate and work with multi-disciplined and multi-site teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's, Master's, or Dual degree in Electrical, Electronics and Communication Engineering, a relevant technical field, or equivalent practical experience. Experience with design concepts and computer hardware architecture. Preferred qualifications: Internship work, work experience, or personal project experience outside the classroom in Hardware, Electrical Engineering or Mechanical Engineering. Experience in one or more of the following areas: SoC/ASIC Design, Design Verification, Physical Design, Design for Testability. Experience with Verilog/HDL or System Verilog coding. About the jobGoogle engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step. Google's Consumer Hardware Silicon division builds chips optimized for Google-branded consumer devices. Our product areas include imaging, machine learning, video, and security. We aim to build a team with talent that resonates with Google's culture of innovation and fun.As a Silicon Engineer, you will design, develop, and deploy consumer hardware. As a member of a fast-paced multi-disciplinary team, you will use your creativity and various range of engineering experience to explore solutions to a variety of engineering problems. Additionally, you will participate in the design, analysis, and prototyping of new concepts. You will also work in a manufacturing and product oriented development environment and collaborate with vendors and outside sources in order to see parts through to manufacture.The ML, Systems, Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.Responsibilities Work with the SoC teams to develop power and performance optimized chips. Contribute to the design, verification, and silicon implementation of ASICs and SoCs. Work on design concepts around CPUs, image processing, machine learning, computer vision, security, and video. Collaborate with teams in automating the SoC design flows. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience in RTL design using Verilog/System Verilog. 8 years of experience in subsystem microarchitecture creation, RTL integration and delivery. Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC, VCLP, synthesis). Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, or a related field. 12 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience in leading subsystem integration and delivery. Experience in micro architecting and generating interconnects/Network on Chip (NOC) for subsystems/SOC. Proficiency in AMBA (Advanced Microcontroller Bus Architecture) protocol (e.g., AXI/APB/AHB/ACE/CHI). Expertise in low power design, power estimation, analysis and optimization. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Collaborate with Architecture teams and define the microarchitecture of complex Subsystems including interface protocols, block diagrams, and data flow. Develop RTL implementations (verilog/system verilog) and create the required subsystem that meets competitive Power, Performance, and Area (PPA) targets. Perform RTL quality checks such as Lint, CDC, RDC, SDC and UPF checks. Participate in debugs with the verification team to ensure a functional design. Own power analysis and optimization for the subsystem, ensuring exceptional PPA. Lead a team of engineers to ensure high quality, on time delivery of subsystems. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.