Design Verification Engineer

RESPONSIBILITIES:

• To be responsible for managing technology in projects and providing technical guidance or solutions for work completion
• To be responsible for providing technical guidance or solutions
• To develop and guide the team members in enhancing their technical capabilities and increasing productivity
• To prepare and submit status reports for minimizing exposure and risks on the project or closure of escalations.
• To ensure process compliance in the assigned module, and participate in technical discussions or review.

BENEFIT:

• 18 paid leaves per year (including 12 annual leaves + 6 personal leaves)
• Insurance plan based on full salary + 13th salary + Performance Bonus.
• 100% full salary in probation period.
• Medical Benefit for Employee and Family.
• Working in a fast paced, flexible, and multinational working environment. Chance to travel onsite (in 49 countries).
• Internal Training (Technical & Functional). Scope of English Training.
• Working time: 8:30 AM-6:00 PM From Mondays to Fridays.

• 5+ years of Experience.
• Bachelors/Masters degree in Electronics /Electrical Engineering with 5+ year’s experience in verification
• Good understanding of ASIC/SoC life cycle
• Experience in OVM/UVM methodologies using SV
• Experience with Full chip test plan development/modification
• Experience with Testbench development/modification , Test case development, coding, execution, bug analysis, Regressions, coverage analysis ,Verification closure
• Experience in prevalent standards & Protocols viz. PCIe Gen3/4/5/USB3/DDR4/5, /Ethernet / CSI2 / I3C / AMBA
• Experience with Gate level simulations
• Experience in scripting
• Should have participated in multiple ASIC/SoC verification till tape out stage
• Good command of English. Have chance to work onsite in Japan.

For support and more information, please contact:

Tap Nguyen (Mr.)

Phone/Zalo: +84 904775776

Email: [email protected]